Embedded Flash Memory Device with Floating Gate Embedded in a Substrate

ABSTRACT

An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No.14/980,147, entitled “Embedded Flash Memory Device with Floating GateEmbedded in a Substrate,” filed on Dec. 28, 2015, which application is adivisional of and claims priority to Ser. No. 13/924,331, filed on Jun.21, 2013, now U.S. Pat. No. 9,230,977, and entitled “An Embedded FlashMemory Device with Floating Gate Embedded in a Substrate,” whichapplications is incorporated herein by reference.

BACKGROUND

Flash memories, which use dielectric trapping layers or floating layersto store charges, are often used in System-On-Chip (SOC) technology, andare formed on the same chip along with other integrated circuits. Forexample, High-Voltage (HV) circuits, Input/output (IO) circuits, corecircuits, and Static Random Access Memory (SRAM) circuits are oftenintegrated on the same chip as the flash memories. The respective flashmemories are often referred to as embedded memories since they areembedded in the chip on which other circuits are formed, as compared tothe flash memories formed on chips that do not have other circuits.Flash memories have structures different from HV circuit devices, IOcircuit devices, core circuit devices, and SRAM circuit devices.Therefore, the embedding of memory devices with other types of devicesfaces challenges when the technology evolves.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the embodiments, and the advantagesthereof, reference is now made to the following descriptions taken inconjunction with the accompanying drawings, in which:

FIGS. 1 through 18 are cross-sectional views of intermediate stages inthe manufacturing of embedded memory devices and other types of devicesin accordance with some exemplary embodiments;

FIGS. 19 and 20 are cross-sectional views of intermediate stages in themanufacturing of embedded memory devices in accordance with someexemplary embodiments, wherein the charge storage layers of a pluralityof embedded memory devices are formed in discrete recesses; and

FIGS. 21 and 22 are cross-sectional views of intermediate stages in themanufacturing of embedded memory devices in accordance with someexemplary embodiments, wherein the charge storage layers of a pluralityof embedded memory devices are formed in a same continuous recess.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the embodiments of the disclosure are discussedin detail below. It should be appreciated, however, that the embodimentsprovide many applicable concepts that can be embodied in a wide varietyof specific contexts. The specific embodiments discussed areillustrative, and do not limit the scope of the disclosure.

An embedded memory device and the methods of forming the same areprovided in accordance with various exemplary embodiments. Theintermediate stages of forming the embedded memory device areillustrated. The variations of the embodiments are discussed. Throughoutthe various views and illustrative embodiments, like reference numbersare used to designate like elements.

Referring to FIG. 1, semiconductor substrate 20, which is a part ofsemiconductor wafer 2, is provided. In some embodiments, semiconductorsubstrate 20 includes crystalline silicon. Other commonly used materialssuch as carbon, germanium, gallium, boron, arsenic, nitrogen, indium,phosphorus, and/or the like, may also be included in semiconductorsubstrate 20. Semiconductor substrate 20 may be a bulk substrate or aSemiconductor-On-Insulator (SOI) substrate. In some exemplaryembodiments, semiconductor substrate 20 comprises Si_(1-z)Ge_(z),wherein value z is the atomic percentage of germanium in SiGe, and maybe any value ranging from, and including, 0 and 1. For example, whenvalue z is 0, semiconductor substrate 20 comprises a crystalline siliconsubstrate. When value z is 1, semiconductor substrate 20 comprises acrystalline germanium substrate. Substrate 20 may also have a compoundstructure including a III-V compound semiconductor on a siliconsubstrate, or a silicon germanium (or germanium) layer on a siliconsubstrate.

Semiconductor substrate 20 includes portions in regions 100, 200, 300,and 400. In accordance with some embodiments, regions 100, 200, 300, and400 include an embedded flash memory region, a High-Voltage (HV) region,an Input/output (IO) region, and a Static Random Access Memory (SRAM)region/general logic device region, respectively. Embedded flash memoryregion 100 is used for forming embedded flash memory cells (such as 156in FIGS. 18, 20, and 22) therein. HV region 200 is used for forming HVdevices (such as 256 in FIG. 18) therein. IO Region 300 is used forforming IO devices (such as 356 in FIG. 18) therein. Core/SRAM Region400 is used for forming core devices and/or SRAM cells (such as 456 inFIG. 18) therein. The core devices, sometimes referred to as logicdevices, do not include any memory array therein, and may be, or may notbe, in the peripheral region of SRAM arrays. For example, the coredevices may be in the driver circuit or the decoder circuit of the SRAMarrays (in region 400) or the flash memory array in region 100. The HVdevices are supplied with, and are configured to endure, a positivepower supply voltage Vdd1 higher than the positive power supply voltageVdd2 of the devices in region SRAM/core region 400. For example, powersupply voltage Vdd2 may be lower than about 1V, and power supply voltageVdd1 may be between about 1.5V and about 3.3V. Although portions ofsubstrate 20 in regions 100, 200, 300, and 400 are shown asdisconnected, they are portions of the same continuous substrate 20.

Referring to FIG. 2, recess 4 is formed in substrate 20, for example, byetching substrate 20. Depth D1 of recess 4 is close to the thickness ofthe charge storage layer 10 (FIG. 5) that is to be formed in recess 4 ina subsequent step. In some exemplary embodiments, depth D1 is betweenabout 100 nm and about 200 nm, although different depths may be adopted.

As shown in FIG. 3, bottom dielectric layer 6 is formed on substrate 20.In some embodiments, bottom dielectric layer 6 is formed of siliconoxide, which may be formed by performing a thermal oxidation onsubstrate 20. In alternative embodiments, bottom dielectric layer 6comprises silicon oxynitride or other dielectric materials that have lowleakage of charges. In some embodiments, thickness T1 of bottomdielectric layer 6 is between about 20 Å and about 50 Å. It isappreciated, however, that the values recited throughout the descriptionare merely examples, and may be changed to different values. Inalternative embodiments, bottom dielectric layer 6 is formed throughdeposition. Bottom dielectric layer 6 may be a conformal layer with thevertical portions and horizontal portions having similar thicknesses,for example, with differences smaller than 20 percent of either one ofthe thicknesses of the vertical portions and horizontal portions.

Referring to FIG. 4, blanket charge storage layer 8 is formed. In someembodiments, charge storage layer 8 is formed of a conductive materialsuch as polysilicon, metal, or the like. In alternative embodiments,charge storage layer 8 is formed of a dielectric material with a hightrap density. In some exemplary embodiment, charge trapping layer 24comprises silicon nitride (SiN). Charge storage layer 8 fills theunfilled portion of recess 4.

Next, referring to FIG. 5, a planarization such as a Chemical MechanicalPolish (CMP) is performed to remove excess portions of charge storagelayer 8. The remaining portion of charge storage layer 8 is referred toas charge storage layer 10 (sometimes referred to as a floating gate)hereinafter. During the CMP, the portions 6A of bottom dielectric layer6, which portions are over substrate 20, are used as a CMP stop layer.Accordingly, the top surface of charge storage layer 10 is coplanar withthe top surface of portions 6A of bottom dielectric layer 6. After theCMP, the top surface 10A of charge storage layer 10 is slightly higherthan top surfaces 20B of substrate portions 200/300/400, with heightdifference AH being between about 5 nm and about 50 nm, for example. Inalternative embodiments, the top surface 10A of charge storage layer 10is slightly lower than top surfaces 20B of substrate portions200/300/400. The majority of charge storage layer 10 may be embedded insubstrate 20, with a small portion over substrate 20. For example,height difference AH may be smaller than about 40 percent of thicknessH1 of charge storage layer 10.

FIG. 6 illustrates the formation of top dielectric layer 12, which maybe a single layer or a composite layer. In some embodiments, topdielectric layer 12 is a single layer, which may be a silicon oxidelayer, a silicon oxynitride layer, or the like. In alternativeembodiments, top dielectric layer 12 is a composite layer comprising aplurality of dielectric layers. For example, FIG. 6 illustrates thatdielectric layer 12 has a triple-layer structure, which may include anOxide-Nitride-Oxide (ONO) structure, with layers 22, 24, and 28 being asilicon oxide layer, a silicon nitride layer, and a silicon oxide layer,respectively.

Referring to FIG. 7, bottom dielectric layer 6 and top dielectric layer12 are patterned in an etching step. The portions of bottom dielectriclayer 6 and top dielectric layer 12 are removed from regions 200, 300,and 400. The portion of bottom dielectric layer 6 and top dielectriclayer 12 in region 100 are left un-removed. After the patterning, asshown in FIG. 8, HV dielectric layer 26 is formed in regions 200, 300,and 400. Thickness T2 of HV dielectric layer 26 may be between about 50Å and about 300 Å.

In accordance with some embodiments, HV dielectric layer 26 is formedusing thermal oxidation by oxidizing substrate 20. Accordingly, HVdielectric layer 26 is formed in regions 200, 300, and 400, and not inregion 100. In alternative embodiments, HV dielectric layer 26 is formedusing a Chemical Vapor Deposition (CVD) method such as Plasma EnhanceCVD (PECVD), Low Pressure CVD (LPCVD), Atomic Layer Deposition (ALD), orthe like. In these embodiments, HV dielectric layer 26 may comprisesilicon oxide, silicon oxynitride, or the like. The dielectric constantof the HV dielectric layer 26 and dielectric layer 28 may be about 3.8in some embodiments.

As shown in FIG. 9, HV dielectric layer 26 is patterned, and is removedfrom regions 300 and 400. Next, Referring to FIG. 10, IO dielectriclayer 30 is formed. In some embodiments, IO dielectric layer 30comprises silicon oxide. Alternatively, IO dielectric layer 30 comprisessilicon oxynitride. Thickness T3 of IO dielectric layer 30 may bebetween about 20 Å and about 70 Å, which may be smaller than thicknessT2 of HV dielectric layer 26 in some embodiments. Similarly, IOdielectric layer 30 may be formed through thermal oxidation of substrate20, deposition, or the like. After the formation of IO dielectric layer30, IO dielectric layer 30 is removed from region 400.

Referring to FIG. 11, interfacial layer 32 is formed on substrate 20.Interfacial layer 32 may comprise a chemical oxide, a thermal oxide, orthe like. In some embodiments, interfacial layer 32 is formed byoxidizing the exposed surface portion of substrate 20. In alternativeembodiments, interfacial layer 32 is formed by treating the surfaceportion of substrate 20 using a chemical, for example, an oxidant suchas ozone water or hydrogen peroxide. The resulting interfacial layer 32is referred to as a chemical oxide layer, which comprises silicon oxide.Thickness T4 of interfacial layer 32 may be between about 8 Å and about20 Å, which may be smaller than thickness T3 of IO dielectric layer 30in some embodiments.

Referring to FIG. 12, high-k dielectric layer 34, capping layer 36, anddummy gate layer 38 are formed sequentially, and are formed in regions100, 200, 300, and 400 simultaneously. Accordingly, each of layers 34,36, and 38 has a same thickness and a same material in regions 100, 200,300, and 400. Dummy gate layer 38 may be formed of polysilicon in someexemplary embodiments. High-k dielectric layer 34 may have a k valuegreater than about 7.0, and may include an oxide or a silicate of Hf,Al, Zr, La, Mg, Ba, Ti, Pb, Yb, Pr, Nd, Gd, Er, Dy, or combinationsthereof. Exemplary materials of high-k dielectric layer 34 includeMgO_(x), BaTi_(x)O_(y), BaSr_(x)Ti_(y)O_(z), PbTi_(x)O_(y),PbZr_(x)Ti_(y)O_(z), and the like, with values X, Y, and Z being between0 and 1. The thickness of high-k dielectric layer 34 may be betweenabout 0.5 nm and about 10 nm. The formation methods of high-k dielectriclayer 34 may include Molecular-Beam Deposition (MBD), Atomic LayerDeposition (ALD), Physical Vapor Deposition (PVD), and the like.

Over high-k dielectric layer 34, capping layer 36 may be formed. In someembodiments, capping layer 36 comprises titanium nitride (TiN). Inalternative embodiments, the exemplary materials of capping layer 36include tantalum-containing materials and/or titanium-containingmaterials such as TaC, TaN, TaA1N, TaSiN, and combinations thereof.Dummy gate layer 38 is then formed over capping layer 36.

FIGS. 13 through 18 illustrate the formation of devices in regions 100,200, 300, and 400 using a gate-last approach, wherein the gates of thedevices are referred to as replacement gates. Referring to FIG. 13,layers 12, 26, 30, 32, 34, 36, and 38 are patterned, forming layerstacks 140, 240, 340, and 440 in regions 100, 200, 300, and 400,respectively. After the patterning, lightly doped source and drainregions (not shown) and/or packet regions (not shown) may be formedadjacent to either one or all layer stacks 140, 240, 340, and 440.

Next, referring to FIG. 14, gate spacers 42 are formed on the sidewallsof layer stacks 140, 240, 340, and 440. In some embodiments, gatespacers 42 comprise silicon nitride, although other dielectric materialsmay also be used. The formation of gate spacers 42 includes forming ablanket layer(s), and performing an anisotropic etching to remove thehorizontal portions of the blanket layer. The remaining portions of theblanket layer form gate spacers 42.

FIG. 15 illustrates the formation of source and drain regions 44, whichare alternatively referred to as a source/drain regions 44 hereinafter.Source/drain regions 44 may be formed through implantation or epitaxy.The formation details of source/drain regions 44 are not discussedherein.

FIG. 16 illustrates the formation of Inter-Layer Dielectric (ILD) 46,which is formed of a dielectric material such as Phospho-Silicate Glass(PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass(BPSG), or the like. ILD 46 has a top surface higher than the topsurface of layer stacks 140, 240, 340, and 440. A CMP may then beperformed to level the top surface of ILD 46 and the top surfaces of thelayer stacks, as shown in FIG. 17.

Referring to FIG. 18, the remaining portions of polysilicon layer 38(FIG. 17) are removed, for example, through etching, and are replacedwith replacement gates. The replacement gates include metal gateelectrodes 152, 252, 352, and 452. Metal gate electrodes 152, 252, 352,and 452 may have a single layer structure or a multi-layer structureincluding a plurality of layers, which is schematically illustratedusing reference notations 148 and 150. Metal gate electrode 152 formsthe gate electrode of embedded flash memory 156. Metal gate electrode252 forms the gate electrode of HV device (transistor) 256. Metal gateelectrode 352 forms the gate electrode of IO device (transistor) 356.Metal gate electrode 452 forms the gate electrode of core or SRAM device(transistor) 456. Gate electrodes 152, 252, 352, and 452 may comprisemetal or metal alloys such as Cu, W, Co, Ru, Al, TiN, TaN, TaC,combinations thereof, and multi-layers thereof. As shown in FIG. 18, thetop surface of metal gate 152 is coplanar with the top surfaces of metalgates 252, 352, and 452 due to the CMP. The bottom surface of metal gate152 is higher than the bottom surfaces of metal gates 252, 352, and 452.

In subsequent steps, contact openings (not shown) are formed in ILD 46,exposing underlying source/drain regions 44. Source/drain silicides andsourced/drain contact plugs (not shown) may be formed to electricallycouple to source/drain regions 44. The formation of memory device 156,HV transistor 256, IO transistor 356, and core/SRAM transistor 456 isthus finished.

In memory region 100, there may be a plurality of memory devices havingthe same structure, for example, the structure of memory device 156 inFIG. 18. The plurality of memory devices 156 may be arranged as an arrayincluding a plurality of rows and columns of the flash memory devices.FIG. 19 illustrates a cross-sectional view of device region 100, inwhich a plurality of memory devices 156 is to be formed. In accordancewith some embodiments, in the recessing of substrate 20, which recessingstep is shown in FIG. 2, discrete recesses 4 are formed. The discreterecesses 4 may form an array in the top view of the structure in FIG.19. Each of the recesses 4 is used to form the charge storage layer ofone of the embedded flash memory devices. The portions of substrate 20between discrete recesses 4 are not etched, and hence have top surfaces20A higher than the bottom surfaces of recesses 4.

In subsequent steps in accordance with these embodiments, the processsteps shown in FIGS. 3 through 18 are performed to form a plurality ofmemory devices 156, and the resulting structure is shown in FIG. 20.Devices 256, 356, and 456 are not shown in FIG. 20, and are the same asin FIG. 18. As shown in FIG. 20, charge storage layers 10 and therespective bottom dielectric layers 6 are formed in discrete recesses 4(FIG. 19) in substrate 20. Substrate 20 thus includes un-etched portionson opposite sides of, and adjacent to, each of charge storage layers 10.In these embodiments, in device region 100, some portions of substrate20 between neighboring devices 156 may have top surfaces 20A (also shownin FIG. 18) that are coplanar with the top surfaces 20B (FIG. 18) of theportions of substrate 20 in regions 200, 300, and 400.

In accordance with alternative embodiments, instead of forming discreterecesses in order to place charge storage layers, the portions ofsemiconductor substrate between recesses 4, which are used for formingcharge storage layers 10 in, are also etched. Hence, the entirety of thesubstrate 20 in device region 100, at which a memory array is to beformed, is recessed. FIG. 21 illustrates a cross-sectional view ofdevice region 100 and recess 4, in which a plurality of memory devices156 is to be formed. In accordance with some embodiments, in therecessing of substrate 20, which step is shown in FIG. 2, a block ofsubstrate in device region 100 is recessed. Dashed line 20B illustrateswhere the top surface of substrate 20 was before the recessing. Thelevel represented by 20B is also the level of the top surfaces of theportions of substrate 20 in regions 200, 300, and 400 (FIG. 18). Therecessed top surface of the portion of substrate 20 in region 100 ismarked as 20A, which is lower than 20B.

In subsequent steps in accordance with these embodiments, the processsteps shown in FIGS. 3 through 18 are performed to form a plurality ofmemory devices 156, and the resulting structure is shown in FIG. 22.Devices 256, 356, and 456 are not shown in FIG. 22, and are the same asin FIG. 18. As shown in FIG. 22, charge storage layers 10 and therespective bottom dielectric layers 6 are formed in recess 4 thatextends throughout a plurality of memory devices 156. Substrate 20 inthese embodiments does not include portions on opposite sides of, andadjacent to, each of charge storage layers 10. Rather, in device region100, charge storage layers 10 and bottom dielectric layers 6 are overtop surface 20A, which is lower than top surface 20B of the portions ofsubstrate 20 in regions 200/300/400 (FIG. 18), wherein top surfaces 20Bare also shown in FIG. 18.

In accordance with the embodiments of the present disclosure, in theembedded flash memory 156 (FIGS. 13 and 16), floating gates are formedat least partially in substrate 20. Since floating gates have greatthicknesses, if floating gates are formed over the substrate, the gatestacks of the embedded flash memory devices will be much higher than thegate stacks of other transistors such as HV transistors, IO transistors,and core/SRAM transistors. This incurs process difficulty. For example,the CMP in the formation of replacement gates cannot be performedbecause this may cause the entire dummy gates of the embedded flashmemory devices to be removed in the CMP. By embedding the floating gatesof the flash memory devices in the substrates, the heights of the gatestacks of the flash memory devices are reduced, and the subsequent CMPmay be performed.

In addition, high-k dielectric layer 34 is formed over the topdielectric layer 12 to form the blocking layer of the resulting embeddedflash memory 156. With the dual layer structure of the blocking layer,the thickness of the high-k dielectric and the top dielectric layer maybe reduced without sacrificing the charge retention ability of thememory devices. On the other hand, with the formation of the metal gatesin the memory device 156, the mismatch between the threshold voltages ofdifferent embedded flash memory devices is reduced. This is advantageousfor the formation of flash memory devices having different thresholdvoltage levels. With small mismatch, different levels of thresholdvoltages may be clearly distinguished from each other.

In accordance with some embodiments, an embedded flash memory deviceincludes a gate stack, which includes a bottom dielectric layerextending into a recess in a semiconductor substrate, and a chargestorage layer over the bottom dielectric layer. The charge storage layerincludes a portion in the recess. The gate stack further includes a topdielectric layer over the charge storage layer, and a metal gate overthe top dielectric layer. Source and drain regions are in thesemiconductor substrate, and are on opposite sides of the gate stack.

In accordance with other embodiments, a gate stack of an embedded flashmemory device includes a bottom silicon oxide layer extending onsidewalls and a bottom of a recess in the semiconductor substrate, and acharge storage layer over the bottom silicon oxide layer. A majority ofthe charge storage layer is embedded in the recess. The gate stackfurther includes a top oxide layer over the charge storage layer, ahigh-k dielectric layer over and contacting the top oxide layer, a metalcapping layer over and contacting the high-k dielectric layer, and ametal gate over the high-k dielectric layer.

In accordance with yet other embodiments, a method includes recessing asemiconductor substrate to form a recess in a device region of thesemiconductor substrate, forming a bottom dielectric layer, wherein thebottom dielectric layer extends on sidewalls and a bottom surface of therecess, forming a charge storage layer over the bottom dielectric layer,wherein a portion of the charge storage layer is in the recess, forminga top dielectric layer over the charge storage layer, forming a metalgate over the top dielectric layer, and forming source and drain regionsin the semiconductor substrate and on opposite sides of the chargestorage layer.

Although the embodiments and their advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the embodiments as defined by the appended claims. Moreover,the scope of the present application is not intended to be limited tothe particular embodiments of the process, machine, manufacture, andcomposition of matter, means, methods and steps described in thespecification. As one of ordinary skill in the art will readilyappreciate from the disclosure, processes, machines, manufacture,compositions of matter, means, methods, or steps, presently existing orlater to be developed, that perform substantially the same function orachieve substantially the same result as the corresponding embodimentsdescribed herein may be utilized according to the disclosure.Accordingly, the appended claims are intended to include within theirscope such processes, machines, manufacture, compositions of matter,means, methods, or steps. In addition, each claim constitutes a separateembodiment, and the combination of various claims and embodiments arewithin the scope of the disclosure.

What is claimed is:
 1. A method comprising: recessing a semiconductorportion of a semiconductor substrate to form a recess in an entirety ofa first memory array region of the semiconductor substrate, thesemiconductor substrate having an upper surface in a non-recessed regionof the semiconductor substrate, wherein a bottom surface of the recessis a surface of the semiconductor substrate; depositing a bottomdielectric layer on the bottom surface of the recess; forming a chargestorage layer over the bottom dielectric layer, wherein a portion of thecharge storage layer is in the recess; planarizing the charge storagelayer and the bottom dielectric layer; forming a top dielectric layerover the charge storage layer, the top dielectric layer being above theupper surface of the semiconductor substrate; forming a metal gate overthe top dielectric layer; and forming a source region and a drain regionin the bottom surface of the recess in the semiconductor substrate andon opposite sides of the charge storage layer to form a memory device,wherein an array of memory devices is formed in the first memory arrayregion when the memory device is formed.
 2. The method of claim 1,wherein the top dielectric layer is a composite layer comprising a firstsilicon oxide layer, a silicon nitride layer, and a second silicon oxidelayer.
 3. The method of claim 1, further comprising: forming a gatespacer contacting both the charge storage layer and the metal gate,wherein the gate spacer comprises a portion extending into the recess.4. The method of claim 1, further comprising forming an inter-layerdielectric extending into the recess.
 5. The method of claim 1, furthercomprising forming a gate spacer, wherein the gate spacer contacts thecharge storage layer and the bottom dielectric layer.
 6. The method ofclaim 1, wherein an entirety of a topmost surface of the top dielectriclayer is above the top surface of the semiconductor substrate.
 7. Themethod of claim 1, further comprising: before forming the metal gate,forming a dummy gate layer over the top dielectric layer.
 8. The methodof claim 7, further comprising after forming the dummy gate layer:forming a gate spacer; and removing the dummy gate layer.
 9. A methodcomprising: etching a semiconductor substrate to form a recess extendinginto the semiconductor substrate; and forming an embedded flash memorydevice comprising: forming a bottom dielectric layer comprising: a firsthorizontal portion over a top surface of the semiconductor substrate; asecond horizontal portion in the recess; and a vertical portionconnecting the first horizontal portion with the second horizontalportion; forming a charge storage layer over the bottom dielectriclayer, with a portion of the charge storage layer in the recess;performing a planarization to level a top surface of the charge storagelayer with a top surface of the bottom dielectric layer; forming a topdielectric layer over the charge storage layer; forming a metal gateover the top dielectric layer; patterning to remove the first horizontalportion of the bottom dielectric layer; and forming a source region anda drain region in the semiconductor substrate and on opposite sides ofthe charge storage layer.
 10. The method of claim 9, wherein the sourceregion and the drain region are isolated from each other by a channel ofthe embedded flash memory device, and the source region and the drainregion extend from a bottom surface of the recessed semiconductorsubstrate into the semiconductor substrate.
 11. The method of claim 9further comprising: after forming the metal gate, forming a gate spacer,the gate spacer comprising a first edge contacting the bottom dielectriclayer and the charge storage layer.
 12. The method of claim 11, whereinthe first edge of the gate spacer further contacts the top dielectriclayer and the metal gate.
 13. The method of claim 9, wherein theembedded flash memory device is comprised in a memory array comprising aplurality of embedded flash memory devices, and wherein an intermediateportion of the semiconductor substrate between two neighboring ones ofthe plurality of embedded flash memory devices remains after the recessis formed.
 14. The method of claim 9, wherein the embedded flash memorydevice is comprised in a memory array comprising a plurality of embeddedflash memory devices, and wherein an intermediate portion of thesemiconductor substrate between two neighboring ones of the plurality ofembedded flash memory devices is part of the recessed semiconductorsubstrate.
 15. The method of claim 9, wherein the patterning to removethe first horizontal portion of the bottom dielectric layer furthercomprises removing the vertical portion of the bottom dielectric layer.16. A method comprising: etching a recess into a semiconductorsubstrate; blanket depositing a bottom dielectric layer, the bottomdielectric layer comprising: a first horizontal portion of the bottomdielectric layer in the recess; a second horizontal portion of thebottom dielectric layer over a non-recessed portion of the semiconductorsubstrate; and a vertical portion of the bottom dielectric layerconnecting the first horizontal portion with the second horizontalportion; forming a charge storage layer over the bottom dielectriclayer, wherein a first portion of the charge storage layer is in therecess and a second portion of the charge storage layer is over thenon-recessed portion of the semiconductor substrate; forming a topdielectric layer over the charge storage layer; and patterning thecharge storage layer and the bottom dielectric layer to form a pluralityof charge storage layers and a plurality of bottom dielectric layers fora plurality of embedded memory devices, the patterning removing thevertical portion of the bottom dielectric layer.
 17. The method of claim16, further comprising forming other semiconductor devices in anon-recessed device region, the non-recessed device region being locatedon the non-recessed portion of the semiconductor substrate.
 18. Themethod of claim 16, further comprising: before patterning the chargestorage layer and the bottom dielectric layer, forming a dummy gatelayer over the top dielectric layer.
 19. The method of claim 18, furthercomprising, after patterning the charge storage layer and the bottomdielectric layer: removing the dummy gate layer; and forming a metalgate over the top dielectric layer.
 20. The method of claim 19, whereinthe top dielectric layer is a composite layer comprising a silicon oxidelayer and a silicon nitride layer.